Multiple Choice Questions (MCQs) Checking
1.
Abstract:
This project is done for such a program where
answers of the questions are fixed. Admin can change the answers but after
setting the answer project will work for those answers. Program is done in HDL.
2. Logic Diagram:
3.
Equivalent ASM Chart:
4.
State Diagram:
5.
Excitation Table:
6.
Verilog Code:
entity project
is
port (
clk: in STD_LOGIC;
x: in STD_LOGIC;
y: out
STD_LOGIC;
z: out
STD_LOGIC);
end project;
architecture
project_arch of project is
SYMBOLIC ENCODED
state machine: Sreg0
type Sreg0_type
is (
S1, S2, S3, S4,
S5, S6, S7, S8, S9
);
attribute
enum_encoding of Sreg0_type: type is ... -- enum_encoding attribute is not
supported for symbolic encoding
signal Sreg0:
Sreg0_type;
begin
----------------------------------------------------------------------
Machine: Sreg0
----------------------------------------------------------------------
Sreg0_machine:
process (clk)
begin
if clk'event and
clk = '1' then
Set default
values for outputs, signals and variables
...
case Sreg0 is
when S1 =>
if x!=4'b1000
then
Sreg0 <= S3;
elsif x==4'b1000
then
Sreg0 <= S2;
end if;
when S2 =>
if x!=4'b1001
then
Sreg0 <= S5;
elsif x==4'b1001
then
Sreg0 <= S4;
end if;
when S3 =>
if x!=4'b1001
then
Sreg0 <= S5;
elsif x==4'b1001
then
Sreg0 <= S4;
end if;
when S4 =>
if x!=4'b1010
then
Sreg0 <= S7;
elsif x==4'b1010
then
Sreg0 <= S6;
end if;
when S5 =>
if x==4'b1010
then
Sreg0 <= S6;
elsif x!=4'b1010
then
Sreg0 <= S7;
end if;
when S6 =>
if x!=4'b0110
then
Sreg0 <= S9;
elsif x==4'b0110
then
Sreg0 <= S8;
end if;
when S7 =>
if x!=4'b0110
then
Sreg0 <= S9;
elsif x==4'b0110
then
Sreg0 <= S8;
end if;
when S8 =>
if x!=4'b1111
then
Sreg0 <= S1;
elsif x==4'b1111
then
Sreg0 <= S1;
end if;
when S9 =>
if x!=4'b1111
then
Sreg0 <= S1;
elsif x==4'b1111
then
Sreg0 <= S1;
end if;
--vhdl_cover_off
when others
=>
null;
--vhdl_cover_on
end case;
end if;
end process;
end project_arch;
7.
Snap Shot of State
Diagram:
